The present invention relates generally to external circuits on multi-layer printed circuit boards and, more specifically, to external circuit layers on multi-layer printed circuit boards on top of thin dielectric layers, and to the manufacture of such devices.
Current processes for producing external circuit layers on printed circuit boards (PCBs), particularly applications requiring thin dielectric layers, tend to produce external circuit layers that are non-planarized or wavy. In the case of circuitry manufactured by sequential build-up technology, the standard dielectric application techniques provide only incomplete planarization of the underlying circuits.
For instance, referring to FIG. 1, there is shown a conventional printed circuit board 10 having a substrate 12. Substrate 12 may comprise a material such as prepreg (fiberglass coated with a dielectric such as an epoxy). A first circuit pattern 14 is disposed on the surface of substrate 12. Dielectric layer 16 applied over first circuit pattern 14 leaves ridges 18 and valleys 19 created by the circuit pattern 14 underneath dielectric layer 16. A copper foil layer 20 placed over the top of dielectric layer 16 has corresponding ridges 18xe2x80x2 and valleys 19xe2x80x2.
In addition, the copper foil layer 20 may only marginally adhere to dielectric layer 16. Both the ridges 18xe2x80x2 in the copper foil layer 20 and the marginal adherence may negatively impact the ability to define fine-line circuitry on the copper foil layer 20. Fine-line circuitry may be connected between layers by micro-viasxe2x80x94very small holes containing conductive material. Micro-vias are commonly manufactured either by photoimaging techniques, laser or plasma ablation, or mechanical drilling. Each technique has certain advantages.
Photoimaging techniques for manufacturing micro-vias are considered less expensive for high volume production. It has previously been demonstrated that photosensitive, cationically polymerizable, epoxy-based resin systems, such as the system sold by Morton Electronic Materials Corporation of Tustin, Calif. under the trade name Morton DynaVia 2000 (formerly Morton LB-404) may be used as permanent photoimageable dielectrics (PID). Such a system is detailed in U.S. Pat. No. 5,264,325 assigned to the assignee of the present invention.
The process for using permanent photoimageable dielectrics generally includes (a) applying the PID, (b) photoimaging vias by exposing the PID to ultraviolet light through a photomask and then developing away unexposed regions with a suitable developer such as butyrolactone or propylene carbonate, (c) curing the PID, (d) roughening the surface, (e) plating a conductive material onto the surface, (f) etching circuitry on top of the conductive material, and (g) finishing the panel by standard techniques known in the art. The panel may have any number of layers of circuitry, in which case steps (a) through (f) may be repeated in sequence as necessary before finishing the panel. During the step of plating with the conductive material, conductive material may seep into the vias to provide an electrical connection between desired levels of circuitry.
It has also been demonstrated that a PID can be laminated onto a substrate and copper foil laminated on top of the PID using conventional lamination presses, as generally described in U.S. Pat. No. 5,665,650 and U.S. Pat. No. 5,670,750, also assigned to the assignee of the present invention. Such a lamination process has demonstrated excellent adhesion of the copper foil to the PID.
Laser or plasma formation of micro-vias is another favorable technique to produce micro-vias quickly and easily. Laser or plasma formation of micro-vias generally comprises laser or plasma ablating the dielectric material that separates the upper and lower layers of circuitry to produce a hole.
Mechanical mechanisms may also be used to drill micro-vias. When mechanical mechanisms are used to make the micro-vias, the mechanical action tends to smear dielectric on the sides of the via. Thus, a further xe2x80x9cde-smearingxe2x80x9d process may be necessary to remove the smeared dielectric from the walls of the vias before conductive material is placed inside the vias.
A via manufacturing line that uses laser or plasma ablation or mechanical drilling provides the advantage of allowing relatively quick re-tooling for new parts, quick turnaround time for small volumes, a wide choice of materials to be used for the via dielectric layer, and simple processing. Disadvantages include the high capital associated with purchasing laser or plasma imaging tools or mechanical drilling equipment and the low throughput for products having a large number of vias. Traditional materials used as dielectrics in multi-layer circuits having micro-vias formed by laser or plasma ablation or mechanical drilling, such as resin-coated copper and prepreg, are not photoimageable.
Because the laser, plasma, and mechanical micro-via processes are used with different dielectric materials than are used for photoimaging processing, a fabricator cannot use a laser, plasma, or mechanical process to produce low-cost, quick-turnaround prototypes of a potential high-volume product that is intended for future mass-production by photoimaging processes. This test data generated on a prototype having micro-vias produced by a laser, plasma, or mechanical drilling technique is not applicable to a mass-produced product having micro-vias produced by a photoimaging technique, because the prototype and the mass-produced product each have different dielectric materials.
Thus, there remains a need in the field for a manufacturing process for multi-layer circuits whereby the same dielectric material may be used for development of both prototype circuits and mass-produced commercial circuits, in which the prototype micro-vias are created by laser or plasma ablation or mechanical drilling and the mass-produced commercial circuit micro-vias are created by photoimaging techniques.
The present invention provides a process for manufacture of a multi-layer circuit board on a substrate having a top side and a bottom side and a first-level circuitry pattern on at least one of the sides. The process comprises the steps of:
a) applying a permanent photoimageable dielectric material over the first-level circuitry pattern;
b) exposing the permanent photoimageable dielectric material to radiation;
c) laminating a layer of conductive metal to the dielectric material;
d) making holes in the layer of conductive metal to uncover portions of the dielectric material and making holes in the dielectric material by mechanical drilling or by laser or plasma ablation to uncover portions of the first-level circuitry pattern; and
e) making a second-level circuitry pattern on the dielectric material including placing a conductive material in the holes to electrically connect the second layer of circuitry and the first layer of circuitry.
The present invention also provides a process for developing a multi-layer circuit board product in which the first step comprises making a prototype multi-layer circuit board having a structure having a substrate with a top side and a bottom side, a first-level circuitry pattern on at least one of the sides, a permanent photoimageable dielectric material over the first-level circuitry pattern, a conductive metal layer over the dielectric material, a second-level circuitry pattern on the dielectric material, and a plurality of vias containing conductive material that electrically connects the second-level circuitry with the first-level circuitry. The process of making the prototype multi-layer circuit board includes fabricating the vias by laser or plasma ablation or by mechanical drilling.
The second step in the development process comprises evaluating the prototype. The third step comprises making a commercialized multi-layer circuit board having a structure and materials of construction identical to the prototype multi-layer circuit board. The process of making the commercialized multi-layer circuit board includes fabricating the vias by a photoimaging technique.
The present invention also provides a multi-layer circuit board comprising a substrate having a top side and a bottom side; a first-level circuitry pattern on at least one of the sides; a dielectric layer over the first-level circuitry pattern; a conductive metal layer over the dielectric layer; a second-level circuitry pattern on the dielectric; and a plurality of vias containing conductive material that electrically connects the second-level circuitry with the first-level circuitry. The dielectric layer is a permanent photoimageable dielectric material suitable, for fabrication of vias by any one of laser ablation, plasma ablation, mechanical drilling, or photoimaging techniques.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, but are not restrictive, of the invention.